TY - JOUR
T1 - The Need for a Wholistic Design Approach When Using Gallium Arsenide Technology
AU - Gilbert, Barry K.
N1 - Funding Information:
This research was supported by contracts MDA903-84-C-0324 and F29601-84-C-0016 from the Defense Advanced Research Projects Agency. The author thanks C. Bates, D. Endry, S. Karwoski, L. Krueger, B. Naused, J. Ryan, M. Samson, D. Schwab, B. Shamblin, R. Thompson, C. Treder, T. Volkman, and S. Zahn, Mayo Foundation, for technical assistance; S. Roosild, DARPA/DSO, for advice and support; E. Doherty and S. Richardson, Mayo Foundation, for preparation of text and figures.
PY - 1987/8
Y1 - 1987/8
N2 - The emerging Gallium Arsenide digital integrated circuit technology is rapidly becoming well enough established that designers of signal and data processors are planning its incorporation into advanced computational engines of all types. An examination of the characteristics of present and future generation GaAs integrated circuits indicates that they will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic board, and chip layout and packaging constraints in a single integrated approach.
AB - The emerging Gallium Arsenide digital integrated circuit technology is rapidly becoming well enough established that designers of signal and data processors are planning its incorporation into advanced computational engines of all types. An examination of the characteristics of present and future generation GaAs integrated circuits indicates that they will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic board, and chip layout and packaging constraints in a single integrated approach.
UR - http://www.scopus.com/inward/record.url?scp=0023399529&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023399529&partnerID=8YFLogxK
U2 - 10.1109/MAES.1987.5005468
DO - 10.1109/MAES.1987.5005468
M3 - Article
AN - SCOPUS:0023399529
SN - 0885-8985
VL - 2
SP - 30
EP - 33
JO - IEEE Aerospace and Electronic Systems Magazine
JF - IEEE Aerospace and Electronic Systems Magazine
IS - 8
ER -