System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications

Michael J. Degerstrom, Benjamin R. Buhrow, Bart O. McCoy, Patrick J. Zabinski, Barry Kent Gilbert, Erik S. Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.

Original languageEnglish (US)
Title of host publicationProceedings - Electronic Components and Technology Conference
Pages513-520
Number of pages8
DOIs
StatePublished - 2008
Event2008 58th Electronic Components and Technology Conference, ECTC - Lake Buena Vista, FL, United States
Duration: May 27 2008May 30 2008

Other

Other2008 58th Electronic Components and Technology Conference, ECTC
CountryUnited States
CityLake Buena Vista, FL
Period5/27/085/30/08

Fingerprint

Printed circuit boards
Insertion losses

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Degerstrom, M. J., Buhrow, B. R., McCoy, B. O., Zabinski, P. J., Gilbert, B. K., & Daniel, E. S. (2008). System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications. In Proceedings - Electronic Components and Technology Conference (pp. 513-520). [4550021] https://doi.org/10.1109/ECTC.2008.4550021

System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications. / Degerstrom, Michael J.; Buhrow, Benjamin R.; McCoy, Bart O.; Zabinski, Patrick J.; Gilbert, Barry Kent; Daniel, Erik S.

Proceedings - Electronic Components and Technology Conference. 2008. p. 513-520 4550021.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Degerstrom, MJ, Buhrow, BR, McCoy, BO, Zabinski, PJ, Gilbert, BK & Daniel, ES 2008, System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications. in Proceedings - Electronic Components and Technology Conference., 4550021, pp. 513-520, 2008 58th Electronic Components and Technology Conference, ECTC, Lake Buena Vista, FL, United States, 5/27/08. https://doi.org/10.1109/ECTC.2008.4550021
Degerstrom MJ, Buhrow BR, McCoy BO, Zabinski PJ, Gilbert BK, Daniel ES. System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications. In Proceedings - Electronic Components and Technology Conference. 2008. p. 513-520. 4550021 https://doi.org/10.1109/ECTC.2008.4550021
Degerstrom, Michael J. ; Buhrow, Benjamin R. ; McCoy, Bart O. ; Zabinski, Patrick J. ; Gilbert, Barry Kent ; Daniel, Erik S. / System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications. Proceedings - Electronic Components and Technology Conference. 2008. pp. 513-520
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