SIGNAL PROCESSOR ARCHITECTURES AND IMPLEMENTATIONS BASED UPON GALLIUM ARSENIDE DIGITAL INTEGRATED CIRCUITS

THE NEED FOR A HOLISTIC DESIGN APPROACH.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An examination of the characteristics of present and future generation GaAs integrated circuits indicated that circuit designers will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic board, and chip layout and packaging constraints in a single integrated approach.

Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting
PublisherIEEE
Pages794-797
Number of pages4
StatePublished - 1986

Fingerprint

Digital integrated circuits
Logic design
Gallium arsenide
Integrated circuits
Packaging
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

SIGNAL PROCESSOR ARCHITECTURES AND IMPLEMENTATIONS BASED UPON GALLIUM ARSENIDE DIGITAL INTEGRATED CIRCUITS : THE NEED FOR A HOLISTIC DESIGN APPROACH. / Gilbert, Barry Kent.

Technical Digest - International Electron Devices Meeting. IEEE, 1986. p. 794-797.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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abstract = "An examination of the characteristics of present and future generation GaAs integrated circuits indicated that circuit designers will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic board, and chip layout and packaging constraints in a single integrated approach.",
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