Maximum likelihood estimation-based SAR ADC

Akshay Jayaraj; Sanjeev Tannirkulam Chandrasekaran; Archana Ganesh; Imon Banerjee; Arindam Sanyal

doi:10.1109/TCSII.2018.2886260

Maximum likelihood estimation-based SAR ADC

Akshay Jayaraj, Sanjeev Tannirkulam Chandrasekaran, Archana Ganesh, Imon Banerjee, Arindam Sanyal

Diagnostic Radiology

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Abstract

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with maximum likelihood estimation (MLE) is presented in this brief. After SAR quantization is finished, the comparator is fired 18 times and the outputs are sent to the estimator for calculation of the residue voltage. The estimator output is subtracted from the SAR output to form the overall output. MLE improves the ADC SNR by more than 8 dB without the need for prior knowledge of SAR noise distribution. A prototype ADC in 65 nm process achieves an average SNR of 64.5 dB at sampling frequency of 1.28 MHz and power supply of 1 V while consuming 5.6 fJ/conversion-step. The estimation accuracy is consistent across voltage and temperature ranges.

Original language	English (US)
Article number	8572763
Pages (from-to)	1311-1315
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	66
Issue number	8
DOIs	https://doi.org/10.1109/TCSII.2018.2886260
State	Published - Aug 2019

Keywords

Successive approximation register (SAR)
analog-to-digital converter (ADC)
maximum likelihood estimation
stochastic ADC

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2018.2886260

Cite this

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title = "Maximum likelihood estimation-based SAR ADC",

abstract = "A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with maximum likelihood estimation (MLE) is presented in this brief. After SAR quantization is finished, the comparator is fired 18 times and the outputs are sent to the estimator for calculation of the residue voltage. The estimator output is subtracted from the SAR output to form the overall output. MLE improves the ADC SNR by more than 8 dB without the need for prior knowledge of SAR noise distribution. A prototype ADC in 65 nm process achieves an average SNR of 64.5 dB at sampling frequency of 1.28 MHz and power supply of 1 V while consuming 5.6 fJ/conversion-step. The estimation accuracy is consistent across voltage and temperature ranges.",

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AU - Ganesh, Archana

AU - Banerjee, Imon

AU - Sanyal, Arindam

PY - 2019/8

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N2 - A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with maximum likelihood estimation (MLE) is presented in this brief. After SAR quantization is finished, the comparator is fired 18 times and the outputs are sent to the estimator for calculation of the residue voltage. The estimator output is subtracted from the SAR output to form the overall output. MLE improves the ADC SNR by more than 8 dB without the need for prior knowledge of SAR noise distribution. A prototype ADC in 65 nm process achieves an average SNR of 64.5 dB at sampling frequency of 1.28 MHz and power supply of 1 V while consuming 5.6 fJ/conversion-step. The estimation accuracy is consistent across voltage and temperature ranges.

AB - A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with maximum likelihood estimation (MLE) is presented in this brief. After SAR quantization is finished, the comparator is fired 18 times and the outputs are sent to the estimator for calculation of the residue voltage. The estimator output is subtracted from the SAR output to form the overall output. MLE improves the ADC SNR by more than 8 dB without the need for prior knowledge of SAR noise distribution. A prototype ADC in 65 nm process achieves an average SNR of 64.5 dB at sampling frequency of 1.28 MHz and power supply of 1 V while consuming 5.6 fJ/conversion-step. The estimation accuracy is consistent across voltage and temperature ranges.

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Maximum likelihood estimation-based SAR ADC

Abstract

Keywords

ASJC Scopus subject areas

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