Interface roughness effects in ultra-thin tunneling oxides

D. Z.Y. Ting, Erik S. Daniel, T. C. McGill

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Advanced MOSFET for ULSI and novel silicon-based devices require the use of ultrathin tunneling oxides where non-uniformity is often present. We report on our theoretical study of how tunneling properties of ultra-thin oxides are affected by roughness at the silicon/oxide interface. The effect of rough interfacial topography is accounted for by using the Planar Supercell Stack Method (PSSM) which can accurately and efficiently compute scattering properties of 3D supercell structures. Our results indicate that while interface roughness effects can be substantial in the direct tunneling regime, they are less important in the Fowler-Nordheim regime.

Original languageEnglish (US)
Pages (from-to)47-51
Number of pages5
JournalVLSI Design
Volume8
Issue number1-4
DOIs
StatePublished - 1998

Keywords

  • Interface roughness
  • Oxide
  • Tunneling
  • Ultrathin

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Ting, D. Z. Y., Daniel, E. S., & McGill, T. C. (1998). Interface roughness effects in ultra-thin tunneling oxides. VLSI Design, 8(1-4), 47-51. https://doi.org/10.1155/1998/23567