Abstract
The worldwide CMOS integrated circuits industry relies on heavily doped silicon wafers as the starting material for chip fabrication; the resulting integrated circuits are confined to the upper few microns of the wafer, which itself is as much as 600-μm thick. These heavily doped silicon substrates are not insulators, but are actually very lossy; a loss tangent of 105 at 1 MHz is a fairly typical characteristic of the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnects into the substrates, existing computer-aided design (CAD) simulation packages fail to provide accurate results in modeling such heavy dielectric losses, because most CAD packages rely on small perturbation methods in the analysis of dielectric losses. In this paper, the problem of computing the electrical behavior of lossy dielectrics is analyzed by the full wave method, and the mutual capacitances of transmission lines above such heavily doped CMOS substrates are computed and compared with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 621-627 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Components Packaging and Manufacturing Technology Part B |
| Volume | 19 |
| Issue number | 3 |
| DOIs | |
| State | Published - Aug 1996 |
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Keywords
- CMOS
- Full wave
- Green's function
- Impedance
- Integral equation
- Reflection
- Transmission
ASJC Scopus subject areas
- Engineering(all)
Cite this
Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses. / Tan, Jilin; Pan, Guang Wen; Lei, Guang Tsai; Gilbert, Barry Kent.
In: IEEE Transactions on Components Packaging and Manufacturing Technology Part B, Vol. 19, No. 3, 08.1996, p. 621-627.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses
AU - Tan, Jilin
AU - Pan, Guang Wen
AU - Lei, Guang Tsai
AU - Gilbert, Barry Kent
PY - 1996/8
Y1 - 1996/8
N2 - The worldwide CMOS integrated circuits industry relies on heavily doped silicon wafers as the starting material for chip fabrication; the resulting integrated circuits are confined to the upper few microns of the wafer, which itself is as much as 600-μm thick. These heavily doped silicon substrates are not insulators, but are actually very lossy; a loss tangent of 105 at 1 MHz is a fairly typical characteristic of the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnects into the substrates, existing computer-aided design (CAD) simulation packages fail to provide accurate results in modeling such heavy dielectric losses, because most CAD packages rely on small perturbation methods in the analysis of dielectric losses. In this paper, the problem of computing the electrical behavior of lossy dielectrics is analyzed by the full wave method, and the mutual capacitances of transmission lines above such heavily doped CMOS substrates are computed and compared with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained.
AB - The worldwide CMOS integrated circuits industry relies on heavily doped silicon wafers as the starting material for chip fabrication; the resulting integrated circuits are confined to the upper few microns of the wafer, which itself is as much as 600-μm thick. These heavily doped silicon substrates are not insulators, but are actually very lossy; a loss tangent of 105 at 1 MHz is a fairly typical characteristic of the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnects into the substrates, existing computer-aided design (CAD) simulation packages fail to provide accurate results in modeling such heavy dielectric losses, because most CAD packages rely on small perturbation methods in the analysis of dielectric losses. In this paper, the problem of computing the electrical behavior of lossy dielectrics is analyzed by the full wave method, and the mutual capacitances of transmission lines above such heavily doped CMOS substrates are computed and compared with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained.
KW - CMOS
KW - Full wave
KW - Green's function
KW - Impedance
KW - Integral equation
KW - Reflection
KW - Transmission
UR - http://www.scopus.com/inward/record.url?scp=0030216633&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030216633&partnerID=8YFLogxK
U2 - 10.1109/96.533905
DO - 10.1109/96.533905
M3 - Article
AN - SCOPUS:0030216633
VL - 19
SP - 621
EP - 627
JO - IEEE Transactions on Components Packaging and Manufacturing Technology Part B
JF - IEEE Transactions on Components Packaging and Manufacturing Technology Part B
SN - 1070-9894
IS - 3
ER -