An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic

Ramkumar Krithivasan, Guofu Niu, John D. Cressler, Steve M. Currie, Karl E. Fritz, Robert A. Reed, Paul W. Marshall, Pamela A. Riggs, Barbara A. Randall, Barry Kent Gilbert

Research output: Contribution to journalArticle

40 Citations (Scopus)

Abstract

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

Original languageEnglish (US)
Pages (from-to)2126-2134
Number of pages9
JournalIEEE Transactions on Nuclear Science
Volume50
Issue number6 I
DOIs
StatePublished - Dec 2003

Fingerprint

single event upsets
Heterojunction bipolar transistors
hardening
logic
Hardening
high speed
Networks (circuits)
Electric power utilization
Flip flop circuits
Space applications
flip-flops
layouts
Circuit simulation
vulnerability
cross coupling
immunity
Transistors
elimination

Keywords

  • Charge collection
  • Circuit modeling
  • Current-steering logic
  • HBT
  • SiGe
  • Single-event effects (SEE)

ASJC Scopus subject areas

  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

Cite this

Krithivasan, R., Niu, G., Cressler, J. D., Currie, S. M., Fritz, K. E., Reed, R. A., ... Gilbert, B. K. (2003). An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic. IEEE Transactions on Nuclear Science, 50(6 I), 2126-2134. https://doi.org/10.1109/TNS.2003.822094

An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic. / Krithivasan, Ramkumar; Niu, Guofu; Cressler, John D.; Currie, Steve M.; Fritz, Karl E.; Reed, Robert A.; Marshall, Paul W.; Riggs, Pamela A.; Randall, Barbara A.; Gilbert, Barry Kent.

In: IEEE Transactions on Nuclear Science, Vol. 50, No. 6 I, 12.2003, p. 2126-2134.

Research output: Contribution to journalArticle

Krithivasan, R, Niu, G, Cressler, JD, Currie, SM, Fritz, KE, Reed, RA, Marshall, PW, Riggs, PA, Randall, BA & Gilbert, BK 2003, 'An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic', IEEE Transactions on Nuclear Science, vol. 50, no. 6 I, pp. 2126-2134. https://doi.org/10.1109/TNS.2003.822094
Krithivasan R, Niu G, Cressler JD, Currie SM, Fritz KE, Reed RA et al. An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic. IEEE Transactions on Nuclear Science. 2003 Dec;50(6 I):2126-2134. https://doi.org/10.1109/TNS.2003.822094
Krithivasan, Ramkumar ; Niu, Guofu ; Cressler, John D. ; Currie, Steve M. ; Fritz, Karl E. ; Reed, Robert A. ; Marshall, Paul W. ; Riggs, Pamela A. ; Randall, Barbara A. ; Gilbert, Barry Kent. / An SEU Hardening Approach for High-Speed SiGe HBT Digital Logic. In: IEEE Transactions on Nuclear Science. 2003 ; Vol. 50, No. 6 I. pp. 2126-2134.
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