Performance of TI high density interconnect for 1 GHz digital MCM applications

Multichip modules have inherent performance advantages over other packaging technologies to which digital designers are turning to meet stringent system performance requirements. However, for designs requiring up to 1 GHz clocks and subnanosecond rise times, a thorough understanding of the multichip module interconnect is essential to fully utilize performance advantages. At these operating speeds, interconnect as short as one inch can limit system performance in a poorly designed module. This paper presents preliminary data from a joint effort between Texas Instruments (TI) and the Mayo Foundation under sponsorship of the Advanced Research Projects Agency (ARPA) which is characterizing the HDI process for use in high speed designs. Results indicate that HDI technology is well suited for use in digital designs that have clock frequencies as high as one gigahertz and subnanosecond rise times with acceptable noise and signal degradation.