PCB pin-field considerations for 40 Gb/s SerDes channels

Michael J. Degerstrom, Devon J. Post, Barry K. Gilbert, Erik S. Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.

Original languageEnglish (US)
Title of host publication2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Pages1392-1400
Number of pages9
DOIs
StatePublished - Sep 9 2013
Event2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States
Duration: May 28 2013May 31 2013

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
CountryUnited States
CityLas Vegas, NV
Period5/28/135/31/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Degerstrom, M. J., Post, D. J., Gilbert, B. K., & Daniel, E. S. (2013). PCB pin-field considerations for 40 Gb/s SerDes channels. In 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 (pp. 1392-1400). [6575755] (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2013.6575755