TY - GEN
T1 - PCB pin-field considerations for 40 Gb/s SerDes channels
AU - Degerstrom, Michael J.
AU - Post, Devon J.
AU - Gilbert, Barry K.
AU - Daniel, Erik S.
PY - 2013
Y1 - 2013
N2 - Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.
AB - Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.
UR - http://www.scopus.com/inward/record.url?scp=84883336073&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883336073&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2013.6575755
DO - 10.1109/ECTC.2013.6575755
M3 - Conference contribution
AN - SCOPUS:84883336073
SN - 9781479902330
T3 - Proceedings - Electronic Components and Technology Conference
SP - 1392
EP - 1400
BT - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
T2 - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Y2 - 28 May 2013 through 31 May 2013
ER -