Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs

Chad M. Smutzer, Michael J. Degerstrom, Barry Kent Gilbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Demanding signal- and power-integrity performance requirements in high-performance computing (HPC) systems require careful trade-space analysis when prioritizing layer allocations in printed circuit board (PCB) designs. Typically, the topmost layers in a stackup construction are the most desirable for enhancing both signal and power delivery capabilities. In this paper, we use analytical performance metrics to determine PCB layer utilization for optimized signal and power performance in sample designs targeting 56 Gbps non-return-to-zero (NRZ) differential signaling and a power delivery network (PDN) providing sub-1 mOhm impedance.

Original languageEnglish (US)
Title of host publication2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509003495
DOIs
StatePublished - Jun 20 2016
Event20th IEEE Workshop on Signal and Power Integrity, SPI 2016 - Turin, Italy
Duration: May 8 2016May 11 2016

Other

Other20th IEEE Workshop on Signal and Power Integrity, SPI 2016
CountryItaly
CityTurin
Period5/8/165/11/16

Fingerprint

Printed circuit boards

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Smutzer, C. M., Degerstrom, M. J., & Gilbert, B. K. (2016). Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs. In 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings [7496274] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SaPIW.2016.7496274

Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs. / Smutzer, Chad M.; Degerstrom, Michael J.; Gilbert, Barry Kent.

2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. 7496274.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Smutzer, CM, Degerstrom, MJ & Gilbert, BK 2016, Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs. in 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings., 7496274, Institute of Electrical and Electronics Engineers Inc., 20th IEEE Workshop on Signal and Power Integrity, SPI 2016, Turin, Italy, 5/8/16. https://doi.org/10.1109/SaPIW.2016.7496274
Smutzer CM, Degerstrom MJ, Gilbert BK. Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs. In 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. 7496274 https://doi.org/10.1109/SaPIW.2016.7496274
Smutzer, Chad M. ; Degerstrom, Michael J. ; Gilbert, Barry Kent. / Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs. 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016.
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