TY - GEN
T1 - Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs
AU - Smutzer, Chad M.
AU - Degerstrom, Michael J.
AU - Gilbert, Barry K.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/6/20
Y1 - 2016/6/20
N2 - Demanding signal- and power-integrity performance requirements in high-performance computing (HPC) systems require careful trade-space analysis when prioritizing layer allocations in printed circuit board (PCB) designs. Typically, the topmost layers in a stackup construction are the most desirable for enhancing both signal and power delivery capabilities. In this paper, we use analytical performance metrics to determine PCB layer utilization for optimized signal and power performance in sample designs targeting 56 Gbps non-return-to-zero (NRZ) differential signaling and a power delivery network (PDN) providing sub-1 mOhm impedance.
AB - Demanding signal- and power-integrity performance requirements in high-performance computing (HPC) systems require careful trade-space analysis when prioritizing layer allocations in printed circuit board (PCB) designs. Typically, the topmost layers in a stackup construction are the most desirable for enhancing both signal and power delivery capabilities. In this paper, we use analytical performance metrics to determine PCB layer utilization for optimized signal and power performance in sample designs targeting 56 Gbps non-return-to-zero (NRZ) differential signaling and a power delivery network (PDN) providing sub-1 mOhm impedance.
UR - http://www.scopus.com/inward/record.url?scp=84980327826&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84980327826&partnerID=8YFLogxK
U2 - 10.1109/SaPIW.2016.7496274
DO - 10.1109/SaPIW.2016.7496274
M3 - Conference contribution
AN - SCOPUS:84980327826
T3 - 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
BT - 2016 IEEE 20th Workshop on Signal and Power Integrity, SPI 2016 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE Workshop on Signal and Power Integrity, SPI 2016
Y2 - 8 May 2016 through 11 May 2016
ER -