Low-Power 2K-Cell SDFL Gate Array and DCFL Circuits Using GaAs Self-Aligned E/D MESFET's

Using GaAs self-aligned gate MESFET's, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.6 ns have been obtained for SDFL operating at 108 üW per gate. DCFL has demonstrated ring-oscillator gate delays of 30 ps and speed-power products as low as 1.1 fJ per gate. A 2K-cell gate array designed with low-power SDFL has demonstrated an 8-bit adder with an add time of 11 ns at 236 mW. Automatic software was used for the placement and routine of the 8-bit adder on the gate array. DCFL divide-by-four circuits designed for 500-MHz operation have demonstrated up to 2.5-GHz operation with a power dissipation of 172 üW per gate at 1-GHz clock frequency. DCFL divide-by-four circuits subjected to 3.4 X 107 rads (Si) and 1 X 1014 N/cm², for total dose and neutron fluence, respectively, have demonstrated only minimal reduction in power and no degradation of circuit performance.