INVESTIGATION OF OPTIMUM INTERCHIP SIGNAL TRANSMISSION PROTOCOLS USING GAAS BFL MSI COMPONENTS WITH VARIOUS I/O PERIPHERIES.

B. K. Gilbert; D. J. Schwab; G. Heimbigner; E. Walton; S. Roosild

INVESTIGATION OF OPTIMUM INTERCHIP SIGNAL TRANSMISSION PROTOCOLS USING GAAS BFL MSI COMPONENTS WITH VARIOUS I/O PERIPHERIES.

B. K. Gilbert, D. J. Schwab, G. Heimbigner, E. Walton, S. Roosild

Physiology & Biomedical Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

A study of optimum approaches to the interconnection of high-clock-rate GaAs components on a large circuit board, including the noise environment created thereby, has been undertaken. The authors discuss the design constraints, fabrication, and measured results of two MSI-complexity GaAs integrated circuits, one synchronous and the other asynchronous, designed specifically to investigate the performance strengths and anomalies of interconnected GaAs digital devices. It is expected that circuit tests will result in a set of design rules for large numbers of GaAs integrated circuits operating together in a high-clock-rate subsystem environment.

Original language	English (US)
Pages	19-22
Number of pages	4
State	Published - Dec 1 1984

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "INVESTIGATION OF OPTIMUM INTERCHIP SIGNAL TRANSMISSION PROTOCOLS USING GAAS BFL MSI COMPONENTS WITH VARIOUS I/O PERIPHERIES.",

abstract = "A study of optimum approaches to the interconnection of high-clock-rate GaAs components on a large circuit board, including the noise environment created thereby, has been undertaken. The authors discuss the design constraints, fabrication, and measured results of two MSI-complexity GaAs integrated circuits, one synchronous and the other asynchronous, designed specifically to investigate the performance strengths and anomalies of interconnected GaAs digital devices. It is expected that circuit tests will result in a set of design rules for large numbers of GaAs integrated circuits operating together in a high-clock-rate subsystem environment.",

author = "Gilbert, {B. K.} and Schwab, {D. J.} and G. Heimbigner and E. Walton and S. Roosild",

year = "1984",

month = dec,

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language = "English (US)",

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AU - Gilbert, B. K.

AU - Schwab, D. J.

AU - Heimbigner, G.

AU - Walton, E.

AU - Roosild, S.

PY - 1984/12/1

Y1 - 1984/12/1

N2 - A study of optimum approaches to the interconnection of high-clock-rate GaAs components on a large circuit board, including the noise environment created thereby, has been undertaken. The authors discuss the design constraints, fabrication, and measured results of two MSI-complexity GaAs integrated circuits, one synchronous and the other asynchronous, designed specifically to investigate the performance strengths and anomalies of interconnected GaAs digital devices. It is expected that circuit tests will result in a set of design rules for large numbers of GaAs integrated circuits operating together in a high-clock-rate subsystem environment.

AB - A study of optimum approaches to the interconnection of high-clock-rate GaAs components on a large circuit board, including the noise environment created thereby, has been undertaken. The authors discuss the design constraints, fabrication, and measured results of two MSI-complexity GaAs integrated circuits, one synchronous and the other asynchronous, designed specifically to investigate the performance strengths and anomalies of interconnected GaAs digital devices. It is expected that circuit tests will result in a set of design rules for large numbers of GaAs integrated circuits operating together in a high-clock-rate subsystem environment.

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INVESTIGATION OF OPTIMUM INTERCHIP SIGNAL TRANSMISSION PROTOCOLS USING GAAS BFL MSI COMPONENTS WITH VARIOUS I/O PERIPHERIES.

Abstract

ASJC Scopus subject areas

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