Implementation of digital circuits in an InP scaled HBT technology

Barbara A. Randall, Daniel J. Schwab, Wayne L. Walters, Ann D. Nielsen, Eric L H Amundsen, Marko M. Sokolich, Young K. Brown, Mark M. Lui, Joseph A. Henige, Barry Kent Gilbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The Mayo Foundation Special Purpose Processor Development Group (Mayo) and HRL Laboratories (HRL) are developing circuits for implementation in an Indium Phosphide (InP) sealed Heterojunction Bipolar Transistor (HBT) technology which has the potential for very high performance analog and digital operation. Preliminary results from HRL show that the fT of the devices can be improved from 90 GHz for the HRL InP standard (2 micron emitter) HBT technology to approximately 180 GHz for this sealed (1 micron emitter) HBT technology. Mayo has designed several digital circuits in this scaled technology, the initial test results for which will be reported in this paper.

Original languageEnglish (US)
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages181-184
Number of pages4
ISBN (Print)0780355865
StatePublished - 1999
EventProceedings of the 199 21st Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium) - Monterey, CA, USA
Duration: Oct 17 1999Oct 20 1999

Other

OtherProceedings of the 199 21st Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium)
CityMonterey, CA, USA
Period10/17/9910/20/99

Fingerprint

Indium phosphide
Digital circuits
Heterojunction bipolar transistors
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Randall, B. A., Schwab, D. J., Walters, W. L., Nielsen, A. D., Amundsen, E. L. H., Sokolich, M. M., ... Gilbert, B. K. (1999). Implementation of digital circuits in an InP scaled HBT technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 181-184). Piscataway, NJ, United States: IEEE.

Implementation of digital circuits in an InP scaled HBT technology. / Randall, Barbara A.; Schwab, Daniel J.; Walters, Wayne L.; Nielsen, Ann D.; Amundsen, Eric L H; Sokolich, Marko M.; Brown, Young K.; Lui, Mark M.; Henige, Joseph A.; Gilbert, Barry Kent.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Piscataway, NJ, United States : IEEE, 1999. p. 181-184.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Randall, BA, Schwab, DJ, Walters, WL, Nielsen, AD, Amundsen, ELH, Sokolich, MM, Brown, YK, Lui, MM, Henige, JA & Gilbert, BK 1999, Implementation of digital circuits in an InP scaled HBT technology. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE, Piscataway, NJ, United States, pp. 181-184, Proceedings of the 199 21st Annual IEEE Gallium Arsenide Integrated Circuit Symposium (IEEE GaAs IC Symposium), Monterey, CA, USA, 10/17/99.
Randall BA, Schwab DJ, Walters WL, Nielsen AD, Amundsen ELH, Sokolich MM et al. Implementation of digital circuits in an InP scaled HBT technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Piscataway, NJ, United States: IEEE. 1999. p. 181-184
Randall, Barbara A. ; Schwab, Daniel J. ; Walters, Wayne L. ; Nielsen, Ann D. ; Amundsen, Eric L H ; Sokolich, Marko M. ; Brown, Young K. ; Lui, Mark M. ; Henige, Joseph A. ; Gilbert, Barry Kent. / Implementation of digital circuits in an InP scaled HBT technology. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Piscataway, NJ, United States : IEEE, 1999. pp. 181-184
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