Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS

S. M. Currie, P. R. Schumacher, Barry Kent Gilbert, E. E. Swartzlander, B. A. Randall

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 μm bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages335-343
Number of pages9
Volume2002-January
ISBN (Print)0769517129
DOIs
StatePublished - 2002
EventIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States
Duration: Jul 17 2002Jul 19 2002

Other

OtherIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
CountryUnited States
CitySan Jose
Period7/17/027/19/02

Fingerprint

Fast Fourier transforms
Random access storage
Application specific integrated circuits

Keywords

  • Application specific integrated circuits
  • Clocks
  • CMOS technology
  • Computer architecture
  • Computer interfaces
  • Design engineering
  • Distributed computing
  • Fast Fourier transforms
  • Pipelines
  • Random access memory

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Currie, S. M., Schumacher, P. R., Gilbert, B. K., Swartzlander, E. E., & Randall, B. A. (2002). Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS. In Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors (Vol. 2002-January, pp. 335-343). [1030732] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2002.1030732

Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS. / Currie, S. M.; Schumacher, P. R.; Gilbert, Barry Kent; Swartzlander, E. E.; Randall, B. A.

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 335-343 1030732.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Currie, SM, Schumacher, PR, Gilbert, BK, Swartzlander, EE & Randall, BA 2002, Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS. in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. vol. 2002-January, 1030732, Institute of Electrical and Electronics Engineers Inc., pp. 335-343, IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002, San Jose, United States, 7/17/02. https://doi.org/10.1109/ASAP.2002.1030732
Currie SM, Schumacher PR, Gilbert BK, Swartzlander EE, Randall BA. Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS. In Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Vol. 2002-January. Institute of Electrical and Electronics Engineers Inc. 2002. p. 335-343. 1030732 https://doi.org/10.1109/ASAP.2002.1030732
Currie, S. M. ; Schumacher, P. R. ; Gilbert, Barry Kent ; Swartzlander, E. E. ; Randall, B. A. / Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS. Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. pp. 335-343
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abstract = "The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 μm bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.",
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