TY - GEN
T1 - Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS
AU - Currie, S. M.
AU - Schumacher, P. R.
AU - Gilbert, B. K.
AU - Swartzlander, E. E.
AU - Randall, B. A.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 μm bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
AB - The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 μm bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
KW - Application specific integrated circuits
KW - CMOS technology
KW - Clocks
KW - Computer architecture
KW - Computer interfaces
KW - Design engineering
KW - Distributed computing
KW - Fast Fourier transforms
KW - Pipelines
KW - Random access memory
UR - http://www.scopus.com/inward/record.url?scp=84948742537&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84948742537&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2002.1030732
DO - 10.1109/ASAP.2002.1030732
M3 - Conference contribution
AN - SCOPUS:84948742537
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 335
EP - 343
BT - Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
A2 - Schreiber, Robert
A2 - Bhattacharyya, Shuvra
A2 - Burgess, Neil
A2 - Schulte, Michael
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
Y2 - 17 July 2002 through 19 July 2002
ER -