High performance computing (HPC) 3 dimensional integrated (3DI) thermal test vehicle validation effort

Stephen Polzer, Wendy Wilkins, Jason Prairie, Barry Kent Gilbert, Clifton R Haider

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As system performance requirements for high performance computing (HPC) systems become more demanding, the need to increase component packaging density to shorten interconnect distances becomes more stringent. One technique for accomplishing this requirement is to implement 3-dimensional heterogeneous integration of system components. In an earlier publication, we described the design of a processor-memory module for a high performance computing (HPC) application space using a 3D integration (3DI) approach [1]. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30 Gb/second SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. Using thermal test chips (TTC), we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The technologies selected - semi-rigid flex, power connectors, land grid array (LGA) attachment with an anisotropic film, and cold plate-based cooling - are all commercially available, which were adapted for the test module. We were able to fabricate and conduct thermal testing of this design. This paper includes an overview of our HPC 3DI thermal test vehicle (3DI TTV) design, and compares test results between measured and simulated temperatures for the TTCs used to emulate both the memory and the processor. Unexpected differences were observed between the measured and simulated results at a corner location on the TTC. After ruling out device and test equipment issues, we discovered a silicon defect that, although it could not be modeled using our standard computational fluid dynamics (CFD) methods, appeared to explain the measured results. A rudimentary finite element analysis (FEA) analysis agreed more closely with the measured results, indicating the need for awareness of possible limitations with assumptions used in our CFD analysis.

Original languageEnglish (US)
Title of host publication33rd Annual Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2017 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-220
Number of pages8
ISBN (Electronic)9781538615317
DOIs
StatePublished - Apr 11 2017
Event33rd Annual Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2017 - San Jose, United States
Duration: Mar 13 2017Mar 17 2017

Other

Other33rd Annual Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2017
CountryUnited States
CitySan Jose
Period3/13/173/17/17

Keywords

  • 3D Packaging
  • Cold-plate cooling
  • High performance computing (HPC)
  • Integrated thermal management
  • Processor-memory module

ASJC Scopus subject areas

  • Instrumentation
  • Electrical and Electronic Engineering

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  • Cite this

    Polzer, S., Wilkins, W., Prairie, J., Gilbert, B. K., & Haider, C. R. (2017). High performance computing (HPC) 3 dimensional integrated (3DI) thermal test vehicle validation effort. In 33rd Annual Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2017 - Proceedings (pp. 213-220). [7896933] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SEMI-THERM.2017.7896933