A GaAs configurable cell array has been fabricated using 1- mu m gate MESFETs on 3-inch GaAs substrates. Depletion-mode MESFETs configured in buffered FET logic (BFL) structures were used to implement the logic cells. The cells are programmable for several logic functions. Placement and routing software was developed. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 fJ to 460 fJ. A 306-cell array (equivalent to approximately 430 NOR gates) occupying a chip area of 2. 0 mm multiplied by 2. 8 mm was fabricated. A 5 multiplied by 5-bit parallel multiplier implemented with this array showed a multiplication time of 6. 5 ns and a power dissipation ranging from 337 mW to 722 mW, corresponding to a cell power of 1. 30 mW/cell to 2. 79 mW/cell. The development of a cell array containing 732 cells implementing an 8 multiplied by 8 multiplier is discussed.
|Original language||English (US)|
|Number of pages||4|
|State||Published - Dec 1 1984|
ASJC Scopus subject areas
- Electrical and Electronic Engineering