FAST-Net optical interconnection prototype characterization

This paper reports progress toward the experimental evaluation of the smart pixel based optical interconnection demonstrator currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype data switching system incorporates 2-D monolithic arrays of high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs) that are solder bump bonded to CMOS circuits. The CMOS circuitry provides the high-speed drivers and receivers, control, and interface functions for the smart pixels. The integrated smart pixel arrays are distributed across a multi-chip substrate. A reflective optical system effects a global interconnection pattern across the multi-chip array by imaging clusters of VCSELs onto clusters of PDs. VCSEL/PD pairs are arrayed in a clustered format with a closest pitch of 250 μm. To achieve the required density and registration accuracy, the smart pixel arrays are positioned on the multi-chip substrate to a 10 μm registration tolerance. The optical system is similarly aligned to achieve 10 μm registration accuracy for the VCSEL/PD cluster images. The packaging issues and approach associated with the prototype are reviewed in this paper. The results suggest that a multi-Terabit/sec optically interconnected switch module is feasible.