FAST-Net optical interconnection prototype characterization

M. W. Haney, M. P. Christensen, P. Milojkovic, J. Rieve, J. Ekman, P. Chandramani, F. Kiamilev, Y. Liu, M. Hibbs-Brenner, E. Strzelecka, G. Fokken, M. Vickberg, Barry Kent Gilbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper reports progress toward the experimental evaluation of the smart pixel based optical interconnection demonstrator currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype data switching system incorporates 2-D monolithic arrays of high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs) that are solder bump bonded to CMOS circuits. The CMOS circuitry provides the high-speed drivers and receivers, control, and interface functions for the smart pixels. The integrated smart pixel arrays are distributed across a multi-chip substrate. A reflective optical system effects a global interconnection pattern across the multi-chip array by imaging clusters of VCSELs onto clusters of PDs. VCSEL/PD pairs are arrayed in a clustered format with a closest pitch of 250 μm. To achieve the required density and registration accuracy, the smart pixel arrays are positioned on the multi-chip substrate to a 10 μm registration tolerance. The optical system is similarly aligned to achieve 10 μm registration accuracy for the VCSEL/PD cluster images. The packaging issues and approach associated with the prototype are reviewed in this paper. The results suggest that a multi-Terabit/sec optically interconnected switch module is feasible.

Original languageEnglish (US)
Title of host publicationAmerican Society of Mechanical Engineers, EEP
Place of PublicationUnited States
PublisherASME
Volume26
StatePublished - 1999
EventInterPACK '99: Pacific RIM/ASME International Intersociety Electronics Photonic Packaging Conference 'Advances in Electronic Packaging 1999' - Maui, HI, USA
Duration: Jun 13 1999Jun 19 1999

Other

OtherInterPACK '99: Pacific RIM/ASME International Intersociety Electronics Photonic Packaging Conference 'Advances in Electronic Packaging 1999'
CityMaui, HI, USA
Period6/13/996/19/99

Fingerprint

Optical interconnects
Switching networks
Surface emitting lasers
Photodetectors
Particle accelerators
Pixels
Optical systems
Switching systems
Substrates
Soldering alloys
Packaging
Switches
Bandwidth
Imaging techniques
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Mechanical Engineering

Cite this

Haney, M. W., Christensen, M. P., Milojkovic, P., Rieve, J., Ekman, J., Chandramani, P., ... Gilbert, B. K. (1999). FAST-Net optical interconnection prototype characterization. In American Society of Mechanical Engineers, EEP (Vol. 26). United States: ASME.

FAST-Net optical interconnection prototype characterization. / Haney, M. W.; Christensen, M. P.; Milojkovic, P.; Rieve, J.; Ekman, J.; Chandramani, P.; Kiamilev, F.; Liu, Y.; Hibbs-Brenner, M.; Strzelecka, E.; Fokken, G.; Vickberg, M.; Gilbert, Barry Kent.

American Society of Mechanical Engineers, EEP. Vol. 26 United States : ASME, 1999.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Haney, MW, Christensen, MP, Milojkovic, P, Rieve, J, Ekman, J, Chandramani, P, Kiamilev, F, Liu, Y, Hibbs-Brenner, M, Strzelecka, E, Fokken, G, Vickberg, M & Gilbert, BK 1999, FAST-Net optical interconnection prototype characterization. in American Society of Mechanical Engineers, EEP. vol. 26, ASME, United States, InterPACK '99: Pacific RIM/ASME International Intersociety Electronics Photonic Packaging Conference 'Advances in Electronic Packaging 1999', Maui, HI, USA, 6/13/99.
Haney MW, Christensen MP, Milojkovic P, Rieve J, Ekman J, Chandramani P et al. FAST-Net optical interconnection prototype characterization. In American Society of Mechanical Engineers, EEP. Vol. 26. United States: ASME. 1999
Haney, M. W. ; Christensen, M. P. ; Milojkovic, P. ; Rieve, J. ; Ekman, J. ; Chandramani, P. ; Kiamilev, F. ; Liu, Y. ; Hibbs-Brenner, M. ; Strzelecka, E. ; Fokken, G. ; Vickberg, M. ; Gilbert, Barry Kent. / FAST-Net optical interconnection prototype characterization. American Society of Mechanical Engineers, EEP. Vol. 26 United States : ASME, 1999.
@inproceedings{c506f4bb6fce45e8b8ab45902b32fe2b,
title = "FAST-Net optical interconnection prototype characterization",
abstract = "This paper reports progress toward the experimental evaluation of the smart pixel based optical interconnection demonstrator currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype data switching system incorporates 2-D monolithic arrays of high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs) that are solder bump bonded to CMOS circuits. The CMOS circuitry provides the high-speed drivers and receivers, control, and interface functions for the smart pixels. The integrated smart pixel arrays are distributed across a multi-chip substrate. A reflective optical system effects a global interconnection pattern across the multi-chip array by imaging clusters of VCSELs onto clusters of PDs. VCSEL/PD pairs are arrayed in a clustered format with a closest pitch of 250 μm. To achieve the required density and registration accuracy, the smart pixel arrays are positioned on the multi-chip substrate to a 10 μm registration tolerance. The optical system is similarly aligned to achieve 10 μm registration accuracy for the VCSEL/PD cluster images. The packaging issues and approach associated with the prototype are reviewed in this paper. The results suggest that a multi-Terabit/sec optically interconnected switch module is feasible.",
author = "Haney, {M. W.} and Christensen, {M. P.} and P. Milojkovic and J. Rieve and J. Ekman and P. Chandramani and F. Kiamilev and Y. Liu and M. Hibbs-Brenner and E. Strzelecka and G. Fokken and M. Vickberg and Gilbert, {Barry Kent}",
year = "1999",
language = "English (US)",
volume = "26",
booktitle = "American Society of Mechanical Engineers, EEP",
publisher = "ASME",

}

TY - GEN

T1 - FAST-Net optical interconnection prototype characterization

AU - Haney, M. W.

AU - Christensen, M. P.

AU - Milojkovic, P.

AU - Rieve, J.

AU - Ekman, J.

AU - Chandramani, P.

AU - Kiamilev, F.

AU - Liu, Y.

AU - Hibbs-Brenner, M.

AU - Strzelecka, E.

AU - Fokken, G.

AU - Vickberg, M.

AU - Gilbert, Barry Kent

PY - 1999

Y1 - 1999

N2 - This paper reports progress toward the experimental evaluation of the smart pixel based optical interconnection demonstrator currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype data switching system incorporates 2-D monolithic arrays of high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs) that are solder bump bonded to CMOS circuits. The CMOS circuitry provides the high-speed drivers and receivers, control, and interface functions for the smart pixels. The integrated smart pixel arrays are distributed across a multi-chip substrate. A reflective optical system effects a global interconnection pattern across the multi-chip array by imaging clusters of VCSELs onto clusters of PDs. VCSEL/PD pairs are arrayed in a clustered format with a closest pitch of 250 μm. To achieve the required density and registration accuracy, the smart pixel arrays are positioned on the multi-chip substrate to a 10 μm registration tolerance. The optical system is similarly aligned to achieve 10 μm registration accuracy for the VCSEL/PD cluster images. The packaging issues and approach associated with the prototype are reviewed in this paper. The results suggest that a multi-Terabit/sec optically interconnected switch module is feasible.

AB - This paper reports progress toward the experimental evaluation of the smart pixel based optical interconnection demonstrator currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype data switching system incorporates 2-D monolithic arrays of high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs) that are solder bump bonded to CMOS circuits. The CMOS circuitry provides the high-speed drivers and receivers, control, and interface functions for the smart pixels. The integrated smart pixel arrays are distributed across a multi-chip substrate. A reflective optical system effects a global interconnection pattern across the multi-chip array by imaging clusters of VCSELs onto clusters of PDs. VCSEL/PD pairs are arrayed in a clustered format with a closest pitch of 250 μm. To achieve the required density and registration accuracy, the smart pixel arrays are positioned on the multi-chip substrate to a 10 μm registration tolerance. The optical system is similarly aligned to achieve 10 μm registration accuracy for the VCSEL/PD cluster images. The packaging issues and approach associated with the prototype are reviewed in this paper. The results suggest that a multi-Terabit/sec optically interconnected switch module is feasible.

UR - http://www.scopus.com/inward/record.url?scp=0033324824&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033324824&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0033324824

VL - 26

BT - American Society of Mechanical Engineers, EEP

PB - ASME

CY - United States

ER -