DESIGN AND PERFORMANCE OF A GAAS 2K GATE ARRAY.

Andrzej Peczalski, Gary Lee, William Betten, Herpertap Somal, Tho Vu, Steve Hanka, Richard Novak, G. Y. Lee, Barry Gilbert, Barbara Naused, Susan Karwoski

Research output: Contribution to journalConference article

2 Scopus citations

Abstract

The circuit performance of Schottky diode FET logic (SDFL) is presented in terms of gate delay, and power and noise margin. Various circuit configurations were experimented with for high speed or low power. A statistical database of FET parameters made it possible to track the process. Automated measurement allowed a large number of circuits to be characterized quickly. An 8-bit multiplier with a gate delay of 4 ns and a gate power of 100 mu W was implemented.

Original languageEnglish (US)
Pages (from-to)517-520
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1986

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Peczalski, A., Lee, G., Betten, W., Somal, H., Vu, T., Hanka, S., Novak, R., Lee, G. Y., Gilbert, B., Naused, B., & Karwoski, S. (1986). DESIGN AND PERFORMANCE OF A GAAS 2K GATE ARRAY. Proceedings of the Custom Integrated Circuits Conference, 517-520.