The circuit performance of Schottky diode FET logic (SDFL) is presented in terms of gate delay, and power and noise margin. Various circuit configurations were experimented with for high speed or low power. A statistical database of FET parameters made it possible to track the process. Automated measurement allowed a large number of circuits to be characterized quickly. An 8-bit multiplier with a gate delay of 4 ns and a gate power of 100 mu W was implemented.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Jan 1 1986|
ASJC Scopus subject areas
- Electrical and Electronic Engineering