The design constraints encountered during the implementation of a mixed gallium arsenide/silicon ECL digital RF memory (DRFM) are described. This unit, which is configured to digitize an analog signal at 1 GHz rates, has served as a test bed for ten separate designs for the high clock rate front and back ends of the DRFM system. Preliminary test results from the GaAs components are presented and discussed.
|Original language||English (US)|
|Number of pages||4|
|State||Published - Dec 1 1985|
ASJC Scopus subject areas
- Electrical and Electronic Engineering