DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS.

Barry Kent Gilbert, Daniel J. Schwab, Lester M. Pastuszyn, Allen Firstenberg, Robert H. Evans

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

The design constraints encountered during the implementation of a mixed gallium arsenide/silicon ECL digital RF memory (DRFM) are described. This unit, which is configured to digitize an analog signal at 1 GHz rates, has served as a test bed for ten separate designs for the high clock rate front and back ends of the DRFM system. Preliminary test results from the GaAs components are presented and discussed.

Original languageEnglish (US)
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
Place of PublicationNew York, NY, USA
PublisherIEEE
Pages173-176
Number of pages4
StatePublished - 1985

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Integrated circuits
Data storage equipment
Fabrication
Emitter coupled logic circuits
Gallium arsenide
Clocks
Silicon

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Gilbert, B. K., Schwab, D. J., Pastuszyn, L. M., Firstenberg, A., & Evans, R. H. (1985). DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 173-176). New York, NY, USA: IEEE.

DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS. / Gilbert, Barry Kent; Schwab, Daniel J.; Pastuszyn, Lester M.; Firstenberg, Allen; Evans, Robert H.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). New York, NY, USA : IEEE, 1985. p. 173-176.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gilbert, BK, Schwab, DJ, Pastuszyn, LM, Firstenberg, A & Evans, RH 1985, DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE, New York, NY, USA, pp. 173-176.
Gilbert BK, Schwab DJ, Pastuszyn LM, Firstenberg A, Evans RH. DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). New York, NY, USA: IEEE. 1985. p. 173-176
Gilbert, Barry Kent ; Schwab, Daniel J. ; Pastuszyn, Lester M. ; Firstenberg, Allen ; Evans, Robert H. / DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). New York, NY, USA : IEEE, 1985. pp. 173-176
@inproceedings{7a3580b60cb24752a5bd88c835f85296,
title = "DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS.",
abstract = "The design constraints encountered during the implementation of a mixed gallium arsenide/silicon ECL digital RF memory (DRFM) are described. This unit, which is configured to digitize an analog signal at 1 GHz rates, has served as a test bed for ten separate designs for the high clock rate front and back ends of the DRFM system. Preliminary test results from the GaAs components are presented and discussed.",
author = "Gilbert, {Barry Kent} and Schwab, {Daniel J.} and Pastuszyn, {Lester M.} and Allen Firstenberg and Evans, {Robert H.}",
year = "1985",
language = "English (US)",
pages = "173--176",
booktitle = "Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)",
publisher = "IEEE",

}

TY - GEN

T1 - DESIGN AND FABRICATION OF A DIGITAL RF MEMORY USING CUSTOM DESIGNED GAAS INTEGRATED CIRCUITS.

AU - Gilbert, Barry Kent

AU - Schwab, Daniel J.

AU - Pastuszyn, Lester M.

AU - Firstenberg, Allen

AU - Evans, Robert H.

PY - 1985

Y1 - 1985

N2 - The design constraints encountered during the implementation of a mixed gallium arsenide/silicon ECL digital RF memory (DRFM) are described. This unit, which is configured to digitize an analog signal at 1 GHz rates, has served as a test bed for ten separate designs for the high clock rate front and back ends of the DRFM system. Preliminary test results from the GaAs components are presented and discussed.

AB - The design constraints encountered during the implementation of a mixed gallium arsenide/silicon ECL digital RF memory (DRFM) are described. This unit, which is configured to digitize an analog signal at 1 GHz rates, has served as a test bed for ten separate designs for the high clock rate front and back ends of the DRFM system. Preliminary test results from the GaAs components are presented and discussed.

UR - http://www.scopus.com/inward/record.url?scp=0022305676&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022305676&partnerID=8YFLogxK

M3 - Conference contribution

SP - 173

EP - 176

BT - Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

PB - IEEE

CY - New York, NY, USA

ER -