Advanced layout parameter extraction and detailed timing simulation of GaAs gate arrays in MagiCAD

This paper discusses the features and function of three specific computer aided design tools contained in the Mayo Graphical Integrated Computer Aided Design (MagiCAD) system, a complete electronic CAD software package optimized for the design and layout of semicustom (i.e., gate array) Gallium Arsenide (GaAs) integrated circuits. The first design tool, the Layout Extractor, processes data from placed and routed gate arrays. The Extractor verifies that the layout represents the original logic design, and calculates the parasitic capacitance of the individual wiring segments in the logic nets after they have been routed. The capacitance information, as calculated by the Layout Extractor, is significant in GaAs work since the delay in signals traveling through the routing is often much greater than the delay of the signals traveling through the gates themselves. Once the capacitance data has been processed by the Layout Extractor, it becomes available to the second CAD tool discussed here, the MagiCAD timing simulation program, Sting. Sting, a digital, event-driven simulator, depends on user generation of C language-like behavioral models for all root nodes to be simulated. Through the use of delays calculated by the Extractor from the actual routing and input pin capacitances, Sting assures that the entire chip design will operate correctly at the intended clock rate. The third design tool is a set of programs allowing simulation of the electromagnetic behavior of integrated circuit packages, circuit boards, and multichip modules exposed to very fast risetime digital signals. The algorithms used by the electromagnetic modeling tools allow the user to simulate the electromagnetic behavior of two and three dimensional interconnects when exposed to frequency components up to 5 gigahertz (GHz). Finally, we will describe ongoing work to link the digital simulation tools with the electromagnetic modeling tools to provide overall system simulation which is accurate for the very short risetime signals typical of very high clock rate digital signal and data processors.