A transistorless-current-mode static RAM architecture

H. J. Levy, E. S. Daniel, T. C. McGill

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

We propose a static memory architecture in which each bit consists of a single two-terminal device that is bistable in current. Current-mode operation of the memory array removes the need for cell-isolation transistors, thus, allowing huge increases in density over inverter-based SRAM and capacitor-based DRAM. Low power consumption and fast read/write speeds are ensured by taking advantage of the exponential nature of the memory's current-voltage characteristic.

Original languageEnglish (US)
Pages (from-to)669-672
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number4
DOIs
StatePublished - Apr 1998
Externally publishedYes

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Random access storage
Data storage equipment
Memory architecture
Dynamic random access storage
Static random access storage
Current voltage characteristics
Transistors
Electric power utilization
Capacitors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A transistorless-current-mode static RAM architecture. / Levy, H. J.; Daniel, E. S.; McGill, T. C.

In: IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, 04.1998, p. 669-672.

Research output: Contribution to journalArticle

Levy, H. J. ; Daniel, E. S. ; McGill, T. C. / A transistorless-current-mode static RAM architecture. In: IEEE Journal of Solid-State Circuits. 1998 ; Vol. 33, No. 4. pp. 669-672.
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