@inproceedings{feee352a71224c4f9bde0fade262744a,
title = "A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols",
abstract = "The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.",
keywords = "FPGA, Galois Counter Mode, high throughput, multiple packets per clock cycle, scalable, segmented bus",
author = "Benjamin Buhrow and Karl Fritz and Barry Gilbert and Erik Daniel",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 ; Conference date: 07-12-2015 Through 09-12-2015",
year = "2016",
month = jan,
day = "25",
doi = "10.1109/ReConFig.2015.7393321",
language = "English (US)",
series = "2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015",
}