A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

Benjamin Buhrow, Karl Fritz, Barry Kent Gilbert, Erik Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.

Original languageEnglish (US)
Title of host publication2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467394062
DOIs
StatePublished - Jan 25 2016
EventInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 - Riviera Maya, Mexico
Duration: Dec 7 2015Dec 9 2015

Other

OtherInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
CountryMexico
CityRiviera Maya
Period12/7/1512/9/15

    Fingerprint

Keywords

  • FPGA
  • Galois Counter Mode
  • high throughput
  • multiple packets per clock cycle
  • scalable
  • segmented bus

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Buhrow, B., Fritz, K., Gilbert, B. K., & Daniel, E. (2016). A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols. In 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 [7393321] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ReConFig.2015.7393321