K GaAs configurable cell array has been fabricated using 1 μm gate MESFET’s on 3 in GaAs substrates Using a planar fabrication technique. Depletion-mode MESFET’s configured in BFL structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 to 460 fJ. A 306 cell array (equivalent to approximately 430 nor gates) occupying a chip area of 2.0X2.8 mm was fabricated. A 5x5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns, and a power dissipation ranging from 337 to 722 mW corresponding to a cell power of 1.30-2.79 mW/cell.
ASJC Scopus subject areas
- Electrical and Electronic Engineering