A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic

Robert N. Deming; Ricardo Zucca; Richard P. Vahrenkamp; L. Daniel Hou; Barbara A. Naused; Barry K. Gilbert

doi:10.1109/JSSC.1984.1052215

A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic

Robert N. Deming, Ricardo Zucca, Richard P. Vahrenkamp, L. Daniel Hou, Barbara A. Naused, Barry K. Gilbert

Physiology & Biomedical Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

K GaAs configurable cell array has been fabricated using 1 μm gate MESFET’s on 3 in GaAs substrates Using a planar fabrication technique. Depletion-mode MESFET’s configured in BFL structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 to 460 fJ. A 306 cell array (equivalent to approximately 430 nor gates) occupying a chip area of 2.0X2.8 mm was fabricated. A 5x5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns, and a power dissipation ranging from 337 to 722 mW corresponding to a cell power of 1.30-2.79 mW/cell.

Original language	English (US)
Pages (from-to)	728-738
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	19
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1984.1052215
State	Published - Oct 1984

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1984.1052215

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title = "A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic",

abstract = "K GaAs configurable cell array has been fabricated using 1 μm gate MESFET{\textquoteright}s on 3 in GaAs substrates Using a planar fabrication technique. Depletion-mode MESFET{\textquoteright}s configured in BFL structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 to 460 fJ. A 306 cell array (equivalent to approximately 430 nor gates) occupying a chip area of 2.0X2.8 mm was fabricated. A 5x5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns, and a power dissipation ranging from 337 to 722 mW corresponding to a cell power of 1.30-2.79 mW/cell.",

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AU - Deming, Robert N.

AU - Zucca, Ricardo

AU - Vahrenkamp, Richard P.

AU - Daniel Hou, L.

AU - Naused, Barbara A.

AU - Gilbert, Barry K.

PY - 1984/10

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N2 - K GaAs configurable cell array has been fabricated using 1 μm gate MESFET’s on 3 in GaAs substrates Using a planar fabrication technique. Depletion-mode MESFET’s configured in BFL structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 to 460 fJ. A 306 cell array (equivalent to approximately 430 nor gates) occupying a chip area of 2.0X2.8 mm was fabricated. A 5x5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns, and a power dissipation ranging from 337 to 722 mW corresponding to a cell power of 1.30-2.79 mW/cell.

AB - K GaAs configurable cell array has been fabricated using 1 μm gate MESFET’s on 3 in GaAs substrates Using a planar fabrication technique. Depletion-mode MESFET’s configured in BFL structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 to 460 fJ. A 306 cell array (equivalent to approximately 430 nor gates) occupying a chip area of 2.0X2.8 mm was fabricated. A 5x5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns, and a power dissipation ranging from 337 to 722 mW corresponding to a cell power of 1.30-2.79 mW/cell.

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A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic

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