State of the art SiGe BiCMOS processes have enabled the development of complex integrated circuits capable of supporting very high speeds (e.g. 100+ Gbps digital). While packaging strategies for lower pin count integrated circuits using thin film ceramic or similar substrates have been utilized widely, the more complex circuits realizable in SiGe technology; require larger numbers of high speed interconnects, presenting new packaging challenges. We have demonstrated a flip-chip attach process, whereby gold stud bumps are applied to silicon integrated circuits with aluminum pads and attached using an ACF (Anisotropic conductive film, Sony FP1708E) interposer to a polvmer-based LCP (Liquid Crystal Polymer) multilayer substrate for high speed (S0+ Gbps) applications. The primary demonstrated interconnect used 60 micron stud bumps on a 150 micron pad pitch; a tighter pad pitch could be realized but was relaxed to compensate for a constrained LCP metal etch process. A design of experiments (DOE) was used to determine an optimum ACF cure temperature of 190° C with 6S80 grams offorce for the attach process. The ACF material was shown to serve as a very robust underfill attach material, with good adhesion to the LCP substrate through temperature cycling up to 245°C. The conductive electrical path (primarily through a thermocompression bond of the gold bump to the aluminum pad with minimal occurrence of conductive material from the ACF), exhibited a per-interconnect loss of 1.2 to 1.7 dB at 40 GHz for the particular geometries used.