A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

Guofu Niu; Ramkumar Krithivasan; John D. Cressler; Pamela A. Riggs; Barbara A. Randall; Paul W. Marshall; Robert A. Reed; Barry Gilbert

doi:10.1109/TNS.2002.805390

A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

Guofu Niu, Ramkumar Krithivasan, John D. Cressler, Pamela A. Riggs, Barbara A. Randall, Paul W. Marshall, Robert A. Reed, Barry Gilbert

Physiology & Biomedical Engineering

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

Original language	English (US)
Pages (from-to)	3107-3114
Number of pages	8
Journal	IEEE Transactions on Nuclear Science
Volume	49 I
Issue number	6
DOIs	https://doi.org/10.1109/TNS.2002.805390
State	Published - Dec 2002

Keywords

Charge collection
Circuit modeling
Current-mode logic
Heterojunction bipolar transistor (HBT)
SiGe
Single event effects

ASJC Scopus subject areas

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

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10.1109/TNS.2002.805390

Cite this

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title = "A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures",

abstract = "The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.",

keywords = "Charge collection, Circuit modeling, Current-mode logic, Heterojunction bipolar transistor (HBT), SiGe, Single event effects",

author = "Guofu Niu and Ramkumar Krithivasan and Cressler, {John D.} and Riggs, {Pamela A.} and Randall, {Barbara A.} and Marshall, {Paul W.} and Reed, {Robert A.} and Barry Gilbert",

note = "Funding Information: Manuscript received August 22, 2002; revised October 17, 2002. This work was supported by DTRA under the Radiation Tolerant Microelectronics Program, NASA-Goddard Space Flight Center (GSFC), Greenbelt, MD, under the Electronics Radiation Characterization (ERC) Program, and the Auburn University CSPAE, Auburn, AL.",

year = "2002",

month = dec,

doi = "10.1109/TNS.2002.805390",

language = "English (US)",

volume = "49 I",

pages = "3107--3114",

journal = "IEEE Transactions on Nuclear Science",

issn = "0018-9499",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

AU - Niu, Guofu

AU - Krithivasan, Ramkumar

AU - Cressler, John D.

AU - Riggs, Pamela A.

AU - Randall, Barbara A.

AU - Marshall, Paul W.

AU - Reed, Robert A.

AU - Gilbert, Barry

N1 - Funding Information: Manuscript received August 22, 2002; revised October 17, 2002. This work was supported by DTRA under the Radiation Tolerant Microelectronics Program, NASA-Goddard Space Flight Center (GSFC), Greenbelt, MD, under the Electronics Radiation Characterization (ERC) Program, and the Auburn University CSPAE, Auburn, AL.

PY - 2002/12

Y1 - 2002/12

N2 - The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

AB - The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

KW - Charge collection

KW - Circuit modeling

KW - Current-mode logic

KW - Heterojunction bipolar transistor (HBT)

KW - SiGe

KW - Single event effects

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A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

Abstract

Keywords

ASJC Scopus subject areas

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