@inproceedings{9207d9857a544f958405305f8c74ff3b,
title = "A clock duty-cycle correction and adjustment circuit",
abstract = "A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs.",
author = "Humble, {James S.} and Zabinski, {Patrick J.} and Gilbert, {Barry K.} and Daniel, {Erik S.}",
year = "2006",
language = "English (US)",
isbn = "1424400791",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
pages = "524+511",
booktitle = "2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers",
note = "2006 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2006 Through 09-02-2006",
}