A clock duty-cycle correction and adjustment circuit

James S. Humble, Patrick J. Zabinski, Barry Kent Gilbert, Erik S. Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
StatePublished - 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 6 2006Feb 9 2006

Other

Other2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period2/6/062/9/06

Fingerprint

Clocks
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Humble, J. S., Zabinski, P. J., Gilbert, B. K., & Daniel, E. S. (2006). A clock duty-cycle correction and adjustment circuit. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [1696273]

A clock duty-cycle correction and adjustment circuit. / Humble, James S.; Zabinski, Patrick J.; Gilbert, Barry Kent; Daniel, Erik S.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006. 1696273.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Humble, JS, Zabinski, PJ, Gilbert, BK & Daniel, ES 2006, A clock duty-cycle correction and adjustment circuit. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 1696273, 2006 IEEE International Solid-State Circuits Conference, ISSCC, San Francisco, CA, United States, 2/6/06.
Humble JS, Zabinski PJ, Gilbert BK, Daniel ES. A clock duty-cycle correction and adjustment circuit. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006. 1696273
Humble, James S. ; Zabinski, Patrick J. ; Gilbert, Barry Kent ; Daniel, Erik S. / A clock duty-cycle correction and adjustment circuit. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2006.
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