A clock duty-cycle correction and adjustment circuit

James S. Humble, Patrick J. Zabinski, Barry K. Gilbert, Erik S. Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs.

Original languageEnglish (US)
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages524+511
StatePublished - Dec 1 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 6 2006Feb 9 2006

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period2/6/062/9/06

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Humble, J. S., Zabinski, P. J., Gilbert, B. K., & Daniel, E. S. (2006). A clock duty-cycle correction and adjustment circuit. In 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 524+511). [1696273] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).