A 6K GaAs Gate Array with Fully Functional LSI Personalization

Andrzej Peczalski, G. Lee, William R. Betten, H. Somal, Mark Plagens, James R. Biard, Ian Burrows, Barry K. Gilbert, Rick L. Thompson, Barbara A. Naused, Susan M. Karwoski, Mark L. Samson, Sharon K. Zahn

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


A 12 X 12 multiplier consisting of 19 000 devices was successfully implemented on a 6000 gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry is proposed and implemented which enables on-chip measurement and fault localization in complex GaAs IC's. The high yield of the multiplier (10 percent) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs non-self-aligned depletion-mode fabrication process.

Original languageEnglish (US)
Pages (from-to)581-590
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Issue number2
StatePublished - Apr 1988

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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