A 6K GaAs Gate Array with Fully Functional LSI Personalization

Andrzej Peczalski; G. Lee; William R. Betten; H. Somal; Mark Plagens; James R. Biard; Ian Burrows; Barry K. Gilbert; Rick L. Thompson; Barbara A. Naused; Susan M. Karwoski; Mark L. Samson; Sharon K. Zahn

doi:10.1109/4.1025

A 6K GaAs Gate Array with Fully Functional LSI Personalization

Andrzej Peczalski, G. Lee, William R. Betten, H. Somal, Mark Plagens, James R. Biard, Ian Burrows, Barry K. Gilbert, Rick L. Thompson, Barbara A. Naused, Susan M. Karwoski, Mark L. Samson, Sharon K. Zahn

Physiology & Biomedical Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A 12 X 12 multiplier consisting of 19 000 devices was successfully implemented on a 6000 gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry is proposed and implemented which enables on-chip measurement and fault localization in complex GaAs IC's. The high yield of the multiplier (10 percent) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs non-self-aligned depletion-mode fabrication process.

Original language	English (US)
Pages (from-to)	581-590
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	23
Issue number	2
DOIs	https://doi.org/10.1109/4.1025
State	Published - Apr 1988

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.1025

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title = "A 6K GaAs Gate Array with Fully Functional LSI Personalization",

abstract = "A 12 X 12 multiplier consisting of 19 000 devices was successfully implemented on a 6000 gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry is proposed and implemented which enables on-chip measurement and fault localization in complex GaAs IC's. The high yield of the multiplier (10 percent) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs non-self-aligned depletion-mode fabrication process.",

author = "Andrzej Peczalski and G. Lee and Betten, {William R.} and H. Somal and Mark Plagens and Biard, {James R.} and Ian Burrows and Gilbert, {Barry K.} and Thompson, {Rick L.} and Naused, {Barbara A.} and Karwoski, {Susan M.} and Samson, {Mark L.} and Zahn, {Sharon K.}",

note = "Funding Information: Manuscript received September 4, 1986; revised August 10, 1987. This work was supported by the Defense Advanced Research Project Agency under Contracts F19601-84-C-0010 with Rockwell International for Honeywell activities and N66001-85-C-0337 for Mayo activities. A. Peczalski, G. Lee, W. R. Betten, and H. %mal are with the Honeywell Systems and Research Center, Minneapolis, MN 55418. M. Plagens, J. R. Biard, and I. Burrows are with the Honeywell Optoelectronics Division, Richardson, TX 75081. B. K. Gilbert, R. L. Thompson, B. A. Naused, S. M. Karwoski, M. L. Samson, and S. K. Zahn are with the Special Purpose Development Group, Mayo Foundation, Rochester, MN 55905. IEEE Log Number 8719245.",

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AU - Biard, James R.

AU - Burrows, Ian

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AU - Naused, Barbara A.

AU - Karwoski, Susan M.

AU - Samson, Mark L.

AU - Zahn, Sharon K.

N1 - Funding Information: Manuscript received September 4, 1986; revised August 10, 1987. This work was supported by the Defense Advanced Research Project Agency under Contracts F19601-84-C-0010 with Rockwell International for Honeywell activities and N66001-85-C-0337 for Mayo activities. A. Peczalski, G. Lee, W. R. Betten, and H. %mal are with the Honeywell Systems and Research Center, Minneapolis, MN 55418. M. Plagens, J. R. Biard, and I. Burrows are with the Honeywell Optoelectronics Division, Richardson, TX 75081. B. K. Gilbert, R. L. Thompson, B. A. Naused, S. M. Karwoski, M. L. Samson, and S. K. Zahn are with the Special Purpose Development Group, Mayo Foundation, Rochester, MN 55905. IEEE Log Number 8719245.

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N2 - A 12 X 12 multiplier consisting of 19 000 devices was successfully implemented on a 6000 gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry is proposed and implemented which enables on-chip measurement and fault localization in complex GaAs IC's. The high yield of the multiplier (10 percent) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs non-self-aligned depletion-mode fabrication process.

AB - A 12 X 12 multiplier consisting of 19 000 devices was successfully implemented on a 6000 gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry is proposed and implemented which enables on-chip measurement and fault localization in complex GaAs IC's. The high yield of the multiplier (10 percent) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs non-self-aligned depletion-mode fabrication process.

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A 6K GaAs Gate Array with Fully Functional LSI Personalization

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