A. Peczalski, G. Lee, W. Betten, H. Somal, M. Plagens, J. R. Biard, I. Burrows, B. K. Gilbert, R. L. Thompson, B. A. Naused, M. Karwoski, M. L. Samson, S. K. Zahn

Research output: Contribution to conferencePaper

2 Scopus citations


A 6000-gate array has been designed, fabricated, and tested as a demonstration vehicle for DARPA's GaAs pilot line program. The design of the array emphasizes manufacturability and functionality over large variations in process parameters and temperature. Meeting the gate delay goal of about 1 ns is also of prime importance, with power dissipation a secondary factor. To demonstrate the achievement of goals, a 12 multiplied by 12 multiplier is personalized on the array. The multiplier and its associated test circuitry consist of more than 19,000 transistors and diodes, making it one of the first GaAs large-scale-integrated circuits. This personalization has been successfully tested and verified and the results correlated to simulation results.

Original languageEnglish (US)
Number of pages4
StatePublished - Dec 1 1986

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Peczalski, A., Lee, G., Betten, W., Somal, H., Plagens, M., Biard, J. R., Burrows, I., Gilbert, B. K., Thompson, R. L., Naused, B. A., Karwoski, M., Samson, M. L., & Zahn, S. K. (1986). 6K GaAs GATE ARRAY WITH FULLY FUNCTIONAL LSI PERSONALIZATION.. 23-26.