3D integrated packaging approach for high performance processor-memory module

S. C. Polzer, W. L. Wilkins, J. L. Fasig, M. J. Degerstrom, Barry Kent Gilbert, E. S. Daniel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected - semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling - are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

Original languageEnglish (US)
Title of host publication46th International Symposium on Microelectronics, IMAPS 2013
PublisherIMAPS-International Microelectronics and Packaging Society
Pages452-457
Number of pages6
StatePublished - 2013
Event46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013 - Orlando, FL, United States
Duration: Sep 30 2013Oct 3 2013

Other

Other46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013
CountryUnited States
CityOrlando, FL
Period9/30/1310/3/13

Fingerprint

Packaging
Data storage equipment
Temperature control
Integrated circuits
Heat flux
Substitution reactions
Cooling
Hot Temperature

Keywords

  • 3D packaging
  • Cold-plate cooling
  • High performance computing (HPC)
  • Integrated thermal management
  • Processor-memory module

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Polzer, S. C., Wilkins, W. L., Fasig, J. L., Degerstrom, M. J., Gilbert, B. K., & Daniel, E. S. (2013). 3D integrated packaging approach for high performance processor-memory module. In 46th International Symposium on Microelectronics, IMAPS 2013 (pp. 452-457). IMAPS-International Microelectronics and Packaging Society.

3D integrated packaging approach for high performance processor-memory module. / Polzer, S. C.; Wilkins, W. L.; Fasig, J. L.; Degerstrom, M. J.; Gilbert, Barry Kent; Daniel, E. S.

46th International Symposium on Microelectronics, IMAPS 2013. IMAPS-International Microelectronics and Packaging Society, 2013. p. 452-457.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Polzer, SC, Wilkins, WL, Fasig, JL, Degerstrom, MJ, Gilbert, BK & Daniel, ES 2013, 3D integrated packaging approach for high performance processor-memory module. in 46th International Symposium on Microelectronics, IMAPS 2013. IMAPS-International Microelectronics and Packaging Society, pp. 452-457, 46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013, Orlando, FL, United States, 9/30/13.
Polzer SC, Wilkins WL, Fasig JL, Degerstrom MJ, Gilbert BK, Daniel ES. 3D integrated packaging approach for high performance processor-memory module. In 46th International Symposium on Microelectronics, IMAPS 2013. IMAPS-International Microelectronics and Packaging Society. 2013. p. 452-457
Polzer, S. C. ; Wilkins, W. L. ; Fasig, J. L. ; Degerstrom, M. J. ; Gilbert, Barry Kent ; Daniel, E. S. / 3D integrated packaging approach for high performance processor-memory module. 46th International Symposium on Microelectronics, IMAPS 2013. IMAPS-International Microelectronics and Packaging Society, 2013. pp. 452-457
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