3D integrated packaging approach for high performance processor-memory module

S. C. Polzer, W. L. Wilkins, J. L. Fasig, M. J. Degerstrom, B. K. Gilbert, E. S. Daniel

Research output: Contribution to conferencePaper

Abstract

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected - semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling - are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.

Original languageEnglish (US)
Pages452-457
Number of pages6
StatePublished - Jan 1 2013
Event46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013 - Orlando, FL, United States
Duration: Sep 30 2013Oct 3 2013

Other

Other46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013
CountryUnited States
CityOrlando, FL
Period9/30/1310/3/13

Keywords

  • 3D packaging
  • Cold-plate cooling
  • High performance computing (HPC)
  • Integrated thermal management
  • Processor-memory module

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Polzer, S. C., Wilkins, W. L., Fasig, J. L., Degerstrom, M. J., Gilbert, B. K., & Daniel, E. S. (2013). 3D integrated packaging approach for high performance processor-memory module. 452-457. Paper presented at 46th Annual IMAPS International Symposium on Microelectronics, IMAPS 2013, Orlando, FL, United States.