1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs

Benjamin R. Buhrow, William J. Goetzinger, Barry K. Gilbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-Targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.

Original languageEnglish (US)
Title of host publication2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
EditorsPeter Athanas, Rene Cumplido, Claudia Feregrino, Ron Sass
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509037070
DOIs
StatePublished - 2016
Event2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 - Cancun, Mexico
Duration: Nov 30 2016Dec 2 2016

Publication series

Name2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016

Other

Other2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
Country/TerritoryMexico
CityCancun
Period11/30/1612/2/16

Keywords

  • 400 GbE
  • anti-replay
  • field-programmable gate arrays
  • high-speed networks
  • multi-port RAM
  • segmented bus

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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