Abstract
As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-Targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.
| Original language | English (US) |
|---|---|
| Title of host publication | 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509037070 |
| DOIs | |
| State | Published - Feb 15 2017 |
| Event | 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 - Cancun, Mexico Duration: Nov 30 2016 → Dec 2 2016 |
Other
| Other | 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 |
|---|---|
| Country | Mexico |
| City | Cancun |
| Period | 11/30/16 → 12/2/16 |
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Keywords
- 400 GbE
- anti-replay
- field-programmable gate arrays
- high-speed networks
- multi-port RAM
- segmented bus
ASJC Scopus subject areas
- Hardware and Architecture
- Computer Networks and Communications
Cite this
1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs. / Buhrow, Benjamin R.; Goetzinger, William J.; Gilbert, Barry Kent.
2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7857190.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs
AU - Buhrow, Benjamin R.
AU - Goetzinger, William J.
AU - Gilbert, Barry Kent
PY - 2017/2/15
Y1 - 2017/2/15
N2 - As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-Targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.
AB - As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-Targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.
KW - 400 GbE
KW - anti-replay
KW - field-programmable gate arrays
KW - high-speed networks
KW - multi-port RAM
KW - segmented bus
UR - http://www.scopus.com/inward/record.url?scp=85015033071&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85015033071&partnerID=8YFLogxK
U2 - 10.1109/ReConFig.2016.7857190
DO - 10.1109/ReConFig.2016.7857190
M3 - Conference contribution
AN - SCOPUS:85015033071
BT - 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -