@inproceedings{aa637636c5b64ef3a8154245e09eeb95,
title = "1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs",
abstract = "As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-Targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.",
keywords = "400 GbE, anti-replay, field-programmable gate arrays, high-speed networks, multi-port RAM, segmented bus",
author = "Buhrow, {Benjamin R.} and Goetzinger, {William J.} and Gilbert, {Barry K.}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 ; Conference date: 30-11-2016 Through 02-12-2016",
year = "2016",
doi = "10.1109/ReConFig.2016.7857190",
language = "English (US)",
series = "2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Peter Athanas and Rene Cumplido and Claudia Feregrino and Ron Sass",
booktitle = "2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016",
}